A formal methodology for automated synthesis of VLSI systems /
Gardado en:
OCLC: | 17797746 |
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Autor Principal: | |
Autor Corporativo: | |
Idioma: | English |
Publicado: |
Linköping, Sweden :
Dept. of Computer and Information Science, Linköping University,
1987.
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Series: | Linköping studies in science and technology. Dissertations ;
no. 170. |
Subjects: | |
Formato: | Thesis Monograph Note that CRL will digitize material from the collection when copyright allows. |
Descrición Física: | xi, 181 p. : ill. ; 24 cm. |
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Bibliografía: | Bibliography: p. [173]-181. |
ISBN: | 9178702259 9789178702251 |
Lugar de Publicación: | Sweden. |