A formal methodology for automated synthesis of VLSI systems /
Sábháilte in:
| OCLC: | 17797746 |
|---|---|
| Príomhchruthaitheoir: | |
| Údar corparáideach: | |
| Teanga: | English |
| Foilsithe / Cruthaithe: |
Linköping, Sweden :
Dept. of Computer and Information Science, Linköping University,
1987.
|
| Sraith: | Linköping studies in science and technology. Dissertations ;
no. 170. |
| Ábhair: | |
| Formáid: | Tráchtas Monograph Note that CRL will digitize material from the collection when copyright allows. |