An array processor design methodology for hard real-time systems /

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Bibliographic Details
OCLC:65631717
Main Author: Jayasinghe, Jayasinghe Arachchige Kapila Sriyantha, 1960-
Corporate Author: Universiteit Twente
Language:English
Published: [S.l. : s.n., 1991]
Subjects:
Parallelle verwerking.
Array processors.
Ontwerpen.
Format:

Thesis Monograph

Note that CRL will digitize material from the collection when copyright allows.

Description
Item Description:Proefschrift Enschede.
Physical Description:X, 161 p. : ill. ; 24 cm.
Bibliography:Met lit.opg., index en een samenvatting in het Nederlands.
ISBN:9090040315
9789090040318
Place of Publication:Netherlands.

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