An array processor design methodology for hard real-time systems /

Shranjeno v:
Bibliografske podrobnosti
OCLC:65631717
Glavni avtor: Jayasinghe, Jayasinghe Arachchige Kapila Sriyantha, 1960-
Korporativna značnica: Universiteit Twente
Jezik:English
Izdano: [S.l. : s.n., 1991]
Teme:
Parallelle verwerking.
Array processors.
Ontwerpen.
Format:

Thesis Monograph

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