An array processor design methodology for hard real-time systems /

Gardado en:
Detalles Bibliográficos
OCLC:65631717
Autor Principal: Jayasinghe, Jayasinghe Arachchige Kapila Sriyantha, 1960-
Autor Corporativo: Universiteit Twente
Idioma:English
Publicado: [S.l. : s.n., 1991]
Subjects:
Parallelle verwerking.
Array processors.
Ontwerpen.
Formato:

Thesis Monograph

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