An array processor design methodology for hard real-time systems /

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Bibliographic Details
OCLC:65631717
Main Author: Jayasinghe, Jayasinghe Arachchige Kapila Sriyantha, 1960-
Corporate Author: Universiteit Twente
Language:English
Published: [S.l. : s.n., 1991]
Subjects:
Parallelle verwerking.
Array processors.
Ontwerpen.
Format:

Thesis Monograph

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