An array processor design methodology for hard real-time systems /

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書目詳細資料
OCLC:65631717
主要作者: Jayasinghe, Jayasinghe Arachchige Kapila Sriyantha, 1960-
企業作者: Universiteit Twente
語言:English
出版: [S.l. : s.n., 1991]
主題:
格式:

Thesis Monograph

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實物特徵
Item Description:Proefschrift Enschede.
實物描述:X, 161 p. : ill. ; 24 cm.
參考書目:Met lit.opg., index en een samenvatting in het Nederlands.
ISBN:9090040315
9789090040318
Place of Publication:Netherlands.