Dyfyniad APA

Jayasinghe, J. A. K. S. (1991). An array processor design methodology for hard real-time systems. s.n..

Dyfyniad Arddull Chicago

Jayasinghe, Jayasinghe Arachchige Kapila Sriyantha. An Array Processor Design Methodology for Hard Real-time Systems. [S.l.: s.n., 1991.

Dyfyniad MLA

Jayasinghe, Jayasinghe Arachchige Kapila Sriyantha. An Array Processor Design Methodology for Hard Real-time Systems. s.n., 1991.

Rhybudd: Mae'n bosib nad yw'r dyfyniadau hyn bob amser yn 100% cywir.