Buchanan, I. (1980). Modelling and verification in structured integrated circuit design.
Chicago-viite (17. p.)Buchanan, Irene. Modelling and Verification in Structured Integrated Circuit Design. 1980.
MLA-viite (8. p.)Buchanan, Irene. Modelling and Verification in Structured Integrated Circuit Design. 1980.
Varoitus: Nämä viitteet eivät aina ole täysin luotettavia.