Dyfyniad APA

Buchanan, I. (1980). Modelling and verification in structured integrated circuit design.

Dyfyniad Arddull Chicago

Buchanan, Irene. Modelling and Verification in Structured Integrated Circuit Design. 1980.

Dyfyniad MLA

Buchanan, Irene. Modelling and Verification in Structured Integrated Circuit Design. 1980.

Rhybudd: Mae'n bosib nad yw'r dyfyniadau hyn bob amser yn 100% cywir.