Logic restructuring for timing optimization in VLSI design /
Saved in:
| OCLC: | 188305952 |
|---|---|
| Main Author: | |
| Corporate Author: | |
| Language: | English |
| Published: |
2007.
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| Format: | Thesis Monograph Note that CRL will digitize material from the collection when copyright allows. |
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| 003 | OCoLC | ||
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| 008 | 071112s2007 gw m 000 0 eng d | ||
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| 082 | 0 | 4 | |a 621.395 |
| 099 | |a P-60066116 | ||
| 100 | 1 | |a Werber, Jürgen. | |
| 245 | 1 | 0 | |a Logic restructuring for timing optimization in VLSI design / |c Jürgen Werber. |
| 260 | |c 2007. | ||
| 300 | |a 107 S. |b graph. Darst. |c 30 cm. | ||
| 336 | |a text |b txt |2 rdacontent. | ||
| 337 | |a unmediated |b n |2 rdamedia. | ||
| 338 | |a volume |b nc |2 rdacarrier. | ||
| 502 | |b doctoral |c Rheinische Friedrich-Wilhelms-Universität in Bonn |d 2007. | ||
| 710 | 2 | |a Universität Bonn. | |
| 752 | |a Germany. | ||
| 907 | |a .b26012558 |b 03-09-22 |c 05-05-08 | ||
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