A formal methodology for automated synthesis of VLSI systems /
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| OCLC: | 17797746 |
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| Main Author: | |
| Corporate Author: | |
| Language: | English |
| Published: |
Linköping, Sweden :
Dept. of Computer and Information Science, Linköping University,
1987.
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| Series: | Linköping studies in science and technology. Dissertations ;
no. 170. |
| Subjects: | |
| Format: | Thesis Monograph Note that CRL will digitize material from the collection when copyright allows. |